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PCIe DIP integration with AVIPs and Hybrid virtual platform reference example to facilitate bring-up and debug
Design for AI and AI for Design
The PCIe protocol is widely used for high-performance connections between CPUs and high-throughput peripherals such as GPUs and AI accelerators. It is often described as “the backbone of AI hardware”.
Many Cadence customers in the EMEA region use PCIe in their designs and need to verify and validate both the hardware and software integration of PCIe Design IP (DIP).
Cadence offers several PCIe solutions, including controller and PHY DIPs supporting advanced speeds (Gen6 and Gen7), Verification IP (VIP) for protocol verification in simulation, Accelerated VIP (AVIP) for verification and validation with the Palladium emulator, and Virtual Bridge and SpeedBridge for application-level validation.
While these solutions are often developed and supported independently, customers typically need to integrate them into a unified environment.
This project proposes to participate in the development of a fully functional PCIe DIP + PCIe AVIP integration example that can serve as a reference platform for customer bring-up activities.
On the bus and CPU side of the DIP, a TLM virtual platform could be used to program the PCIe controller and potentially run an operating system with a PCIe driver. The virtual platform can be connected to the RTL DIP through AXI AVIP bridges. The RTL may run on Xcelium, Palladium, or Protium. Ultimately, PCIe enumeration should execute on the operating system and discover the PCIe AVIP endpoints.
AI-based techniques may be applied throughout the project, including the development of RTL wrappers or glue logic, connection verification, or the generation of helpful assertions, using Chipstack technology.
In addition to the core functionality, the following areas can be explored:
Debuggability : provide mechanisms to extract meaningful information at various stages of the PCIe bring-up, for visualization and debug in Verisium Debug, possibly with the AI debug assistant (provide PCIe visibility and knowledge to the assistant). Check what exists for PCIe VIP and evaluate if it is applicable to PCIe AVIP.
Performance monitoring and analysis : send the PCIe transactions to SystemVIP/SPA (System Performance Analyzer), along with AXI transactions and check which meaningful performance metrics can be extracted.
Any additional innovative ideas related to PCIe integration are welcome. The most impactful innovations may lead to patents, publications, or trade secrets.
Possible further extensions :
consider integration of PCIe Virtual Bridge (natural extension of PCIe AVIP), PCIe SpeedBridge (completely replacing the AVIP)
evaluate how the approach is applicable to other high-speed protocols.