At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Design Systems Inc. is looking for a motivated Software Engineer I: VIP to work with us in Belo Horizonte, Brazil.
At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.
As a Software Engineer I you will be part of Verification IP team in the memory modeling group in Belo Horizonte, Brazil.
To understand more on what we do, you can visit Simulation VIP | Cadence
Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world.
Job Description:
- Testing, validating, and deploying enhancements on cutting edge hardware device models for key customer.
- Working with Research and Development (R&D) to develop, implement, and test features for the next generation of Verification IP tools.
- Troubleshoot and resolve complex technical issues related to memory verification, including simulation failures, coverage gaps and performance bottlenecks.
- Provide clear and concise explanations of technical concepts and solutions to customers with varying levels of expertise.
- Support customer project needs including reproduce and fixing their issues in-house to facilitate debugging and resolution.
- Ability to establish a close working relationship with both customers, peers and management
Requirements:
- Complete bachelor’s in computer science or computer Engineering or equivalent experience.
- Experience with Software development: 2 years
- Knowledge and experience with Object-oriented programming.
- Solid advanced data structures and algorithms knowledge.
- Knowledge of C/C++ programming language.
- Experience with Unix environment
- Very good spoken and written English and Portuguese.
Nice to have:
- Working experience on memories like DDR, LPDDR, HBM, and GDDR
- Knowledge of functional verification using SV/UVM.
- Be able to analyze waveform data, simulation logs, and coverage reports to identify and diagnose issues.
- Knowledge/Experience EDA and VLSI design, including Verilog and VHDL languages.
- Experience developing software using version control systems.
- Experience with scripting environments - either Tcl or Python.
Additional Job Details:
- Employment category: CLT
- Employment term: 40 hours/week.
- Hybrid work.
- Competitive benefits.
- Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil.
About Cadence Design Systems:
Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.