Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Junior SoC Design Verification Engineer, you will develop and execute efficient verification strategies ranging from planning and constrained random testing to debugging and closure while collaborating with engineers to validate digital designs across the life-cycle.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
- Plan verification of digital design blocks by understanding specifications and collaborating with design engineers to identify key scenarios.
- Develop and refine constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs using SVA and formal tools.
- Identify and define all relevant coverage measures to address design corner-cases.
- Debug tests with design engineers to ensure functionally correct design blocks.
- Close coverage gaps to identify verification holes and demonstrate progress towards tape-out.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 1 year of experience with using verification components and environments in standard verification methodology.
- Experience verifying digital systems using standard Internet Protocol (IP) components/interconnects such as microprocessor cores, hierarchical memory subsystems.
- Experience verifying digital logic at Register-Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Array (FPGAs) or ASICs.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with verification techniques and verification life-cycle.
- Experience with performance verification of ASICs and ASIC components.
- Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 1 year of experience with using verification components and environments in standard verification methodology.
- Experience verifying digital systems using standard Internet Protocol (IP) components/interconnects such as microprocessor cores, hierarchical memory subsystems.
- Experience verifying digital logic at Register-Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Array (FPGAs) or ASICs.